The present invention generally concerns an integrated image sensor and a method for operating such an integrated image sensor. More particularly, the present invention concerns an integrated image sensor in CMOS technology with increased dynamic. Such CMOS image sensors are particularly intended for making integrated photographic and videos devices.
Owing to current integration technology, it is possible to make an operational image capturing device in integrated form. Such an integrated image capturing device incorporates, on the same chip, a photo-sensor component formed of a set of photo-sensor elements typically organised in the form of a matrix, and a processing component for assuring the operations of capturing images and reading the data captured by the photo-sensor component.
Traditionally, integrated image capturing devices rely on charge transfer techniques. According to these techniques, photo-generated charges are collected and transferred in a determined manner. The most common charge transfer techniques use CCD (charge-coupled device) components or CID (charge injection device) components. Although these devices utilising these components have found numerous commercial applications, they nonetheless have serious drawbacks. In particular, these components rely on non-standard manufacturing techniques, which are, in particular, incompatible with standard CMOS manufacturing processes. Such components are thus obstacles, in terms of costs and manufacturing ease, to the total integration of image sensors.
As a complement to the aforementioned techniques, a concept has been developed around the use of p-n semiconductor junctions as photo-sensor elements, these junctions being commonly called photodiodes. The essential advantage of such elements is their perfect compatibility with standard CMOS manufacturing processes. Solutions relying on photodiodes as photo-sensor elements are known from the prior art, in particular from the document “A Random Access Photodiode Array for Intelligent Image Capture” by Orly Yadid-Pecht, Ran Ginosar and Yosi Shacham Diamand, IEEE Transactions On Electron Devices, Vol. 38, no. 8, August 1991, pp. 1772-1780, incorporated by reference herein.
This document thus discloses an integrated image sensor in CMOS technology in the form of a single chip. The architecture of the sensor, which is similar to that of RAM memories, is illustrated in FIG. 1. This sensor, generally indicated by the reference numeral 1, includes a matrix 10 of pixels arranged in M lines and N columns. This matrix 10 occupies most of the surface of the sensor. A particular pixel of matrix 10 is read by addressing the corresponding line and column. For this purpose the sensor further includes a line addressing circuit 20 coupled to the lines of matrix 10 and an output bus 30 coupled to the columns of matrix 10, both controlled by a control circuit 40.
Each pixel of matrix 10 has a structure conforming to the illustration of FIG. 2a. The pixel, indicated generally by the reference numeral 50 in FIG. 2a, includes a photo-sensor element PD, a first stage A1, storage means C1 and a second stage A2, The photo-sensor element PD is formed of a reverse biased photodiode which typically operates by collecting the electrons photo-generated during a so-called integration period. First stage A1 is a sample and hold type circuit for sampling, at a determined time, the voltage value present across the terminals of photodiode PD. This sampled value is stored on storage means C1 which is typically formed of a capacitor. It will be noted that the voltage value stored on capacitor C1 depends on the transfer function of first stage A1 and in particular on the ratio between the value of the capacitance of photodiode PD and the capacitance of storage means C1. Second stage A2 enables the sampled voltage stored on storage means C1 to be read. The structure schematically described in FIG. 2a advantageously allows separation of the detection and reading processes.
The general structure of the pixel illustrated in FIG. 2a thus enables an electronic shutter function to be achieved, simultaneously allowing all the pixels of the sensor to be exposed and the signal representing this exposure to be stored in each pixel, for subsequent reading. By means of this structure, one can thus make an image sensor capable of taking snap-shots of a scene, i.e. a sensor perfectly suited to capturing images of objects which are moving with respect to the sensor.
Various embodiments are envisaged and presented in the aforementioned prior art document. FIG. 2b shows, in particular, one of these embodiments wherein pixel 50 includes reverse biased photodiode PD and five n-MOS type transistors M1 to M5. Each pixel 50 includes a memory node, designated B, formed of a capacitor (capacitance C1) and protected from the light, for example by a metal protective layer.
According to the aforementioned article, the pixel operates in an integration mode and transistor M1 initialises photodiode PD at a determined voltage before each integration period. Transistor M2 samples the charge accumulated by photodiode PD and stores the signal thereby sampled at the memory node B. Transistor M2 also ensures isolation or uncoupling of photodiode PD and memory node B. Transistor M3 initialises, in particular, memory node B at a determined voltage. Transistor M4 is a source follower transistor and transistor M5 is a line selection transistor and, during the read process, transfers voltage from transistor M4 to an output bus common to all the pixels in a column. The signals applied to this structure include a high supply voltage VDD and a low supply voltage VSS forming ground, a first initialisation signal TI, a coupling signal SH, a second initialisation signal RST, and a line selection signal RSEL.
A first terminal of photodiode PD is connected to ground VSS and the other terminal is connected to the source terminals of transistors M1 and M2 whose gate terminals are respectively controlled by signals TI and SH. The connection node between photodiode PD and the source terminals of transistors M1 and M2 will be designated by the reference A in the following description. The drain terminals of transistors M1, M3 and M4 are connected to the high supply voltage VDD. The second initialisation signal RST is applied to the gate terminal of transistor M3. The source terminal of transistor M3, the drain terminal of transistor M2 and the gate terminal of transistor M4 are together connected to memory node B of the pixel. The source terminal of transistor M4 is connected, via line selection transistor M5, to the output bus common to all the pixels in a column. The line selection signal RSEL is applied to the gate terminal of transistor M5.
It will be noted that most of the CMOS image sensors adopt a rolling shutter technique, i.e. exposure is effected line after line. Such non-simultaneous exposure inevitably leads to image distortion, in particular when a moving image is captured.
The structure of the pixel illustrated in FIGS. 2a and 2b is typically operated in accordance with an integration mode, i.e. the photo-sensor elements are all first of all initialised at a determined voltage and then subjected to illumination during a determined period of time, the charges produced by the photo-sensor elements being accumulated or integrated during this period. According to this operating mode, the pixel response can be termed linear. One drawback of this operating mode lies in the fact that the pixel dynamic range is reduced.
Numerous applications require wide dynamic range image sensors. In order to increase the dynamic range of an image sensor, using sensors including pixels with a logarithmic type response is already known. FIG. 3 shows a diagram of such a pixel arranged to have a logarithmic response. This pixel, globally indicated by the reference numeral 50, includes a reverse biased photodiode PD, and a first and second n-MOS type transistor Q1 and Q2. A first terminal of photodiode PD is connected to ground VSS and its other terminal is connected to the source terminal of transistor Q1. The gate and drain terminals of transistor Q1 are together connected to a supply potential VDD. In this configuration, a low intensity current (of the order of fA to nA), generated by photodiode PD passes through transistor Q1, which is connected as a resistor, and consequently operates in weak inversion or subthreshold conduction. The voltage VOS at the terminals of photodiode PD, at the connection node between photodiode PD and transistor Q1, consequently has logarithmic dependence with respect to the current generated via the effect of illumination. Transistor Q2 forms a pixel read stage (similar to transistor M4 of FIG. 2b) and its gate terminal is connected to the connection node between photodiode PD and transistor Q1.
The configuration illustrated in FIG. 3 is called a continuous conversion configuration, i.e. the voltage VOS, which is a logarithmic function of the current generated by photodiode PD, is directly converted and is representative of the pixel illumination. Unlike the linear response pixel structures, the charges produced by the photo-sensor element are not “integrated” during a so-called integration or period or exposure of determined duration.
One problem of the configuration illustrated in FIG. 3 lies in the fact that the voltage variation produced as a function of illumination tends to be relatively low (of the order of several hundreds of mV). This makes the use of such a pixel difficult for implementing a sensor with a high signal over noise ratio, in particular for reduced illumination levels. Further, the response time of this type of pixel becomes very long for low illuminations where the photo-generated current is low.
Thus the document entitled “Wide-Dynamic-Range Pixel With Combined Linear and Logarithmic Response and Increased Signal Swing”, Eric C. Fox et al., Sensors and Camera Systems for Scientific, Industrial and Digital Photography Applications, Proceedings of SPIE Vol. 3965 (2000), pp. 4-10, has also proposed a pixel structure having a combined linear-logarithmic response. A diagram of this pixel is shown in FIG. 4.
Unlike the pixel of FIG. 3, this pixel further includes a third transistor Q3 connected via its source terminal to the connection node between photodiode PD and first transistor Q1 and, via its drain terminal, to a so-called initialisation or reset potential VBIAS. The conduction state of transistor Q3 is controlled by the signal ΦRST applied to its gate terminal. The initialisation potential VBIAS is higher than supply voltage VDD so that when signal ΦRST is at the high logic state, the voltage VOS at the terminals of photodiode PD is brought to a voltage such that the gate-source voltage of transistor Q1 is less than the voltage necessary to allow subthreshold conduction of transistor Q1.
As soon as signal ΦRST is returned to a low logic level, voltage VOS decreases linearly via the effect of illumination until the gate-source voltage of transistor Q1 reaches a level such that the transistor operates in weak inversion. Beyond this level, the pixel response becomes logarithmic in a similar way to that mentioned already with reference to FIG. 3.
Like the structure illustrated in FIG. 3, the voltage VOS at the terminals of photodiode PD is directly applied to the input of the read stage. It is thus not possible to use these structures directly to make an electronic shutter image sensor suitable for taking snap-shots.